B4860NXN7QUMD

MPU QorIQ RISC 64Bit 667MHz 1V/1.2V/1.35V/1.5V/1.8V/2.5V 1020Pin FCPBGA Tray

Overview

The QorIQ® Qonverge B4860 system-on-chip is designed for next-generation, multi-standard wireless base stations. Based on 28 nm process technology, the B4860 offers unequaled throughput and capacity and integrates a compelling blend of efficient and high-performance programmable cores, as well as application-specific accelerators to deliver optimal power and cost. It targets macro cell base station designs for broadband wireless infrastructure and builds upon the proven success of our multicore CPUs and DSPs in wireless infrastructure markets.

The B4860 combines four 64-bit, dual-threaded e6500 cores built on Power Architecture® technology, six StarCore® SC3900FP Fixed/Floating-Point DSP cores and MAPLE-B baseband acceleration processing engines. It is designed to adapt to the rapidly changing and expanding standards of LTE FDD and TDD, LTE-Advanced including 3GPP LTE Rel.10/11 and WCDMA, and supports different standards simultaneously.

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## Features

### Core Complex

* Four dual-threaded e6500 cores built on Power Architecture® technology up to 1.8 GHz with AltiVec® 128-bit SIMD engine

* Six SC3900FP Fixed/Floating-point DSP cores built on StarCore® technology up to 1.2 GHz, each delivering 38.4 GMacs/Core for Fixed Point or 19.2 GFlops/Core for Floating Point

### Accelerators and Memory Controllers

* Datapath Acceleration Architecture for packet parsing, classifying and distribution

* Queue manager and buffer manager for simplified sharing of network interfaces and hardware accelerators and management of buffer pools

* Multi-accelerator platform engine for baseband MAPLE-B for LTE, LTE-Advanced and WCDMA HSPA/HSPA+

* Two DDR3/3L SDRAM 1.8 GHz 64-bit memory controllers with ECC and interleaving support with attached 512 KB L3 cache

* Integrated security acceleration SEC 5.x

* Enhanced secure digital host controller SD/MMC

* Four I²C controllers

* Enhanced Serial Peripheral Interface eSPI

* Integrated flash controller supporting NAND and NOR flash and general SRAM

* Trust Architecture with secured boot

### Basic Peripherals and Interconnect

* CoreNet® – internal switch fabric delivering full cache coherent system

* Four UART controllers

* Two serial RapidIO® 2.0 controllers each x4 ports running at up to 5G

* Four ports PCI Express® 1.1/2.0 controllers at up to 5G

* Eight Aurora trace interfaces

* One high-speed USB 2.0 controllers

* GPIOs

* 32-bit timers

* JTAG - Test Access Port TAP and Boundary Scan Architecture compliant with IEEE® Std. 1149.1™ and 1149.6™

### Networking and Antenna interfaces

* Eight CPRI 4.2 controllers running at up to 9.8G

* High-speed interfaces multiplexed into 16 SERDES 10G ports

* Up to two Ethernet interfaces supporting 10G/2.5G/1G with IEEE® 1588v2 support

* Up to six Ethernet interfaces supporting 2.5G/1G with IEEE® 1588v2 support

### Package

* FC-PBGA, 33 mm x 33 mm, 1020 pins, 1 mm pitch, Pb-free