74AUP2G07GW

Buffer, AUP/ULP/V Series, 2-Func, 1-Input, CMOS, PDSO6

The is a low-power dual non-inverting Buffer with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 to 3.6V. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 to 3.6V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

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High noise immunity

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IOFF circuitry provides partial power-down mode operation

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Complies with JEDEC standards

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Low static power consumption, ICC = 0.9µA maximum

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Latch-up performance exceeds 100mA per JESD 78 class II

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Inputs accept voltages up to 3.6V

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Low noise overshoot and undershoot <10% of VCC