74AUP1G58GW

NXP  74AUP1G58GW  多功能逻辑门, AUP系列, 可配置, 3输入, 4 mA, 800mV至3.6V, SOT-363-6

The is a low-power Configurable Multiple-function Gate. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND or, NAND, NOR, XOR, inverter and buffer. All inputs can be connected to VCC or GND. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 to 3.6V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G58 has Schmitt-trigger inputs making it capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.

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High noise immunity

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ESD Protection - HBM JESD22-A114F >5000V, MM JESD22-A115-A >200V, CDM JESD22-C101E >1000V

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0.9µA Low static power consumption ICC

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Latch-up performance exceeds 100mA per JESD 78 Class II

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Inputs accept voltages up to 3.6V

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<10% of VCC Low noise overshoot and undershoot

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IOFF circuitry provides partial power-down mode operation