74LVC841APW,112

NXP  74LVC841APW,112  芯片, 锁存器, D型, 透明, 三态, TSSOP-24

The 74LVC841APW is a 10-bit transparent D Latch with 5V tolerant inputs/outputs. It features separate D-type inputs for each latch and 3-state outputs for bus applications. A latch enable pin LE input and an output enable pin OE\\ input are common to all internal latches. The device consists of ten transparent latches with 3-state true outputs. When pin LE is high, data at the Dn inputs enters the latches. In this condition, the latches are transparent, that is, a latch output changes each time its corresponding D-input changes. When pin LE is low, the latches store the information that was present at the D-inputs a set-up time preceding the high to low transition of pin LE. When pin OE\ is low, the contents of the ten latches are available at the outputs. When pin OE\ is high, the outputs go to the high-impedance OFF-state. Operation of the pin OE\ input does not affect the state of the latches. Inputs can be driven from either 3.3 or 5V devices.

.

CMOS low power consumption

.

Direct interface with TTL levels

.

Flow-through pinout architecture