MC10131

双D型主从触发器 Dual TYPE D Master-Slave Flip-Flop

The is a dual master–slave type D flip–flop. Asynchronous Set S and Reset R override Clock CC and Clock Enable CE inputs. Each flip–flop may be clocked separately by holding the common clock in the low state and using the enable inputs for the clocking function. If the common clock is to be used to clock the flip–flop, the Clock Enable inputs must be in the low state. In this case, the enable inputs perform the function of controlling the common clock.

• PD = 235 mW typ/pkg No Load

• FTog = 160 MHz typ

• tpd = 3.0 ns typ

• tr, tf = 2.5 ns typ 20%–80%