74LVC16373ADGG,112

NXP  74LVC16373ADGG,112  芯片, 锁存器, D型, 透明, 三态, TSSOP-48

The 74LVC16373ADGG is a 16-bit transparent D Latch features separate D-type inputs for bus-oriented applications. One LE input and one OE\ are provided for each octal. Inputs can be driven from either 3.3 or 5V devices. When disabled, up to 5.5V can be applied to the outputs. These features allow the use of this device in mixed 3.3 and 5V applications. The device consists of two sections of eight D-type transparent latches with 3-state true outputs. When LE is high, data at the Dn inputs enter the latches. In this condition, the latches are transparent, that is, the latch outputs change each time its corresponding D-input changes. The latches store the information that was present at the D-inputs one set-up time tsu preceding the high-to-low transition of LE. When OE\ is low, the contents of the eight latches are available at the outputs. When OE\ is high, the outputs go to the high impedance OFF-state.

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CMOS low power consumption

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Multibyte flow-through standard pinout architecture

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Multiple low inductance supply pins for minimum noise and ground bounce

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Direct interface with TTL levels