74AUP1G08GW

低功耗的2输入端与门 Low-power 2-input AND gate

The is a low-power 2-input AND Gate, Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 to 3.6V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 to 3.6V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

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High noise immunity

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Complies with JEDEC standards - JESD8-12, JESD8-11, JESD8-7, JESD8-5, JESD8-B

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ESD Protection - HBM JESD22-A114F >5000V, MM JESD22-A115-A >200V, CDM JESD22-C101E >1000V

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0.9µA Low static power consumption ICC

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Latch-up performance exceeds 100mA per JESD 78 Class II

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Inputs accept voltages up to 3.6V

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<10% of VCC Low noise overshoot and undershoot

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IOFF circuitry provides partial power-down mode operation