说明：
1脚：通常连接到目标板的vdd，用来检测目标系统是否供电；检测原理上图中有简单的说明。
2脚：原版的JLink这个引脚没有使用，不提供Vsupply输出，而很多改造版的JLink通过跳线选择从该引脚输出3.3V的电压给外边，我的就是这样的。
可以到网上找JLink的原理图看看。
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0517b/Cjaeccji.html
JTAG interface signals
The following table describes the signals on the JTAG interfaces:
Table1.JTAG signals
| Signal |
I/O |
Description |
| GACK |
- |
This pin is connected in the RVI run control unit, but is not supported in the current release of the software. It is reserved for compatibility with other equipment to be used as a debug acknowledge signal from the target system. It is recommended that this signal is pulled LOW on the target. |
| DBGRQ |
- |
This pin is connected in the RVI run control unit, but is not supported in the current release of the software. It is reserved for compatibility with other equipment to be used as a debug request signal to the target system. The RVI software maintains this signal as LOW. When applicable,RVI uses the scan chain 2 of the processor to put the processor in debug state. It is recommended that this signal is pulled LOW on the target. |
| GND |
|
