电容阵列布局
时间：2022-09-05 22:00:00
目前遇到的数据集：
ADC / DAC
Charge-Scaling DAC, SAR ADC
| 论文题目 | 年份 | 主要内容 | 引用 |
|---|---|---|---|
| 自动生成具有任何电容比的共质心电容阵列 | 2002 | 由氧化物梯度引起的失配模型 | D. Sayed and M. Dessouky, “Automatic generation of common-centroid capacitor arrays with arbitrary capacitor ratio,” Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, 2002, pp. 576-580, doi: 10.1109/DATE.2002.998358. |
| 电容相关性对混合信号/模拟集成电路成品率的提高有影响 | 2008 | 整体相关系数(离散度) | P. Luo, J. Chen, C. Wey, L. Cheng, J. Chen and W. Wu, “Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 11, pp. 2097-2101, Nov. 2008, doi: 10.1109/TCAD.2008.2006139. |
| 在模拟集成电路中考虑系统和随机失配 | 2011 | 对序列 模拟退火，整数比 | C. Lin, J. Lin, Y. Chiu, C. Huang and S. Chang, “Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits,” 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011, pp. 528-533. |
| 考虑虚拟电容器任意比率电容器阵列的失配感知公共质心的放置 | 2012 | 同上，任意整数比,dummy, 方形结论 | C. Lin, J. Lin, Y. Chiu, C. Huang and S. Chang, “Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 12, pp. 1789-1802, Dec. 2012, doi: 10.1109/TCAD.2012.2204993. |
| 电荷缩放 DAC 生成中二进制加权电容器的自动公共质心布局 | 2012 | 考虑0.18um布线，真实性能 | W. Hsiao, Y. He, M. P. Lin, R. Chang and S. Lee, “Automatic common-centroid layout generation for binary-weighted capacitors in charge-scaling DAC,” 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012, pp. 173-176, doi: 10.1109/SMACD.2012.6339445. |
| 二进制加权电容器阵列的公共质感布局和布线 | 2022 | 分类Spiral Chess BC 等，考虑布线和通孔电阻，12nm新工艺【与上一篇论文混淆了我的天】 | Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar, “Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays”, 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.166-171, 2022. |
| 使用多种加权方法 SAR ADC 放置二进制加权电容阵列 | 2014 | 规则布局，星形布线简单，2011年实验对比SA，效果更好 | Y. Li, Z. Zhang, D. Chua and Y. Lian, “Placement for Binary-Weighted Capacitive Array in SAR ADC Using Multiple Weighting Methods,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 9, pp. 1277-1287, Sept. 2014, doi: 10.1109/TCAD.2014.2323217. |
| 基于非线性最坏情况分析的电荷缩放 DAC 新的棋盘放置和尺寸调整方法 | 2016 | 棋盘法，实验比以前好，分散布线太难(不重要) | F. Burcea, H. Habal and H. E. Graeb, “A New Chessboard Placement and Sizing Method for Capacitors in a Charge-Scaling DAC by Worst-Case Analysis of Nonlinearity,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 9, pp. 1397-1410, Sept. 2016, doi: 10.1109/TCAD.2015.2511146. |
| 电荷分级DAC二元加权电容器的寄生感知尺寸及详细布线 | 2014 | 更详细的背景可以看到 | M. P. Lin, V. W. Hsiao and C. Lin, “Parasitic-aware sizing and detailed routing for binary-weighted capacitors in charge-scaling DAC,” 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 2014, pp. 1-6, doi: 10.1109/DAC.2014.6881492. |
| 共质心电容器布局生成考虑器件匹配和寄生最小化 | 2013 | 目前比较完整的布局布线方案，布线需要细看 布线遵循 [7] 中的指南。 | M. P. Lin, Y. He, V. W. Hsiao, R. Chang and S. Lee, “Common-Centroid Capacitor Layout Generation Considering Device Matching and Parasitic Minimization,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 7, pp. 991-1002, July 2013, doi: 10.1109/TCAD.2012.2226457. |
| 回顾未来之路 | 2022 | 有源无源器件的布局 综述 | Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar, “Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead”, 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.114-121, 2022. |
| 系统电容匹配误差和校正布局程序 | 1994 | 12个指导原则 | M. J. McNutt, S. Lemarquis and J. L. Dunkly, “Systematic capacitance matching errors and corrective layout procedures”, IEEE J. Solid-State Circuits, vol. 29, no. 5, pp. 611-616, May 1994. |
| 最新成果：用于模拟和混合信号布局设计的自动自适应 MOM 电容器单元生成 | 2020 | MOM结构 提出新结构 使用上面MPLin布局布线 | T. -W. Wang, P. -C. Wu and M. P. -H. Lin, “Late Breaking Results: Automatic Adaptive MOM Capacitor Cell Generation for Analog and Mixed-Signal Layout Design,” 2020 57th ACM/IEEE Design Automation Conference (DAC), 2020, pp. 1-2, doi: 10.1109/DAC18072.2020.9218609. |
| 用于提高开关电容器电路良率的基于公共质心的单元电容器的最佳布局 | 2013 | 新的相关模型评价指数 新的布局 | C.-C. Huang, C. L. Wey, J.-E. Chen and P.-W. Luo, “Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits”, ACM Trans. Design Autom. Electron. Syst., vol. 19, no. 1, Dec. 2013. |
| 逐次逼近寄存器 ADC 的性能驱动单元电容器布局 | 2015 | 在2013工作基础上，给出布线的指南 | [6] C.-C. Huang, C. L. Wey, J.-E. Chen and P.-W. Luo, “Performance-driven unit-capacitor placement of successive-approximation-register ADCs”, ACM Trans. Design Autom. Electron. Syst., vol. 21, no. 1, Nov. 2015. |
| PACES：二进制加权单元电容器阵列的基于分区中心的对称布局 | 2017 | 棋盘分区布局 | C. -C. Huang, J. -E. Chen and C. -L. Wey, “PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 1, pp. 134-145, Jan. 2017, doi: 10.1109/TCAD.2016.2561403. |
| 基于ILP公式的比例电容阵列集成布局布线 2016 | 2016 | 整数线性规划 | P.-Y. Chou et al., “An Integrated Placement and Routing for Ratioed Capacitor Array based on ILP Formulation”, Proc. VLSI-DAT, pp. 1-4, 2016. |
| 2012 | 550+引用 | J. L. McCreary and P. R. Gray, “All-MOS charge redistribution analog-to-digital conversion techniques. I,” in IEEE Journal of Solid-State Circuits, vol. 10, no. 6, pp. 371-379, Dec. 1975, doi: 10.1109/JSSC.1975.1050629. |
