MC100EP195BFAG

ON SEMICONDUCTOR  MC100EP195BFAG  PROG DELAY LINE, 2.2NS, LQFP-32 新

The MC100EP195B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure 2. The delay increment of the EP195B has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D9:0 values and controlled by the LEN pin 10. A LOW level on LEN allows a transparent LOAD mode of real time delay values by D9:0. A LOW to HIGH transition on LEN will LOCK and HOLD current values present against any subsequent changes in D10:0. The approximate delay values for varying tap numbers correlating to D0 LSB through D9 MSB are shown in Table 6 and Figure 3.

Features

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Maximum Input Clock Frequency >1.2 GHz Typical

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Programmable Range: 0 ns to 10 ns

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Delay Range: 2.2 ns to 12.2 ns

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10 ps Increments

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PECL Mode Operating Range:VCC = 3.0 V to 3.6 V with VEE = 0 V

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NECL Mode Operating Range:VCC = 0 V with VEE = 3.0 V to 3.6 V

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IN/INb Inputs Accept LVPECL, LVNECL, LVDS Levels

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A Logic High on the EN Pin Will Force Q to Logic Low

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D10:0 Can Select Either LVPECL, LVCMOS, or LVTTL Input Levels

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VBB Output Reference Voltage