GS882Z18CGB-200I

SRAM Chip Sync Dual 2.5V/3.3V 9M-Bit 512K x 18 6.5ns/3ns 119Pin F-BGA Tray

* FT pin for user-configurable flow through or pipeline operation * Single/Dual Cycle Deselect selectable * IEEE 1149.1 JTAG-compatible Boundary Scan * On-chip read parity checking; even or odd selectable * ZQ mode pin for user-selectable high/low output drive * 2.5 V or 3.3 V +10%/–10% core power supply * 2.5 V or 3.3 V I/O supply * LBO pin for Linear or Interleaved Burst mode * Internal input resistors on mode pins allow floating mode pins * Default to SCD x18/x36 Interleaved Pipeline mode * Byte Write BW and/or Global Write GW operation * Internal self-timed write cycle * Automatic power-down for portable applications * JEDEC-standard 119- and 165-bump BGA packages * 4th Generation, Green 14 mm x 22 mm, 119 BGA