AD9684BBPZRL7-500
ADC Dual Pipelined 500MSPS 14Bit Serial 196Pin BGA T/R
Product Details
The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9684 is optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs, supporting a variety of user selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate by 2 block.
The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters DDCs. Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator NCO, and three half-band decimation filters supporting a divide by factor of two, four, and eight.
**Applications**
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- Communications
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- Diversity multi-band, multi-mode digital receivers
3G/4G, TD-SCDMA, WCDMA, MC-GSM, LTE
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- General-purpose software radios
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- Ultrawideband satellite receiver
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- Instrumentation spectrum analyzers, network analyzers, integrated RF test solutions
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- Radar
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- Digital oscilloscopes
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- High speed data acquisition systems
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- DOCSIS CMTS upstream receive paths
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- HFC digital reverse path receivers
### Features and Benefits
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- LVDS digital outputs
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- 1.1 W total power per channel at 500MSPS default settings
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- SFDR = 85 dBc at 170MHz fIN 500MSPS
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- SNR = 68.6 dBFS at 170MHz fIN 500MSPS
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- ENOB = 10.9 bits at 170 MHz fIN
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- DNL = ±0.5 LSB
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- INL = ±2.5 LSB
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- Noise Density = -153 dBFS/Hz at 500 MSPS
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- 1.25V, 2.50 V and 3.3V supply operation
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- No missing codes
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- Internal analog-to-digital converter ADC voltage reference
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- See data sheet for additional features
