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DSP Fixed-Point 16Bit 100MHz 257Pin BGA MICROSTAR

Introduction

This section describes the main features, gives a brief functional overview of the TMS320VC5471, lists the pin assignments, and provides a signal description table. The data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data section describing the available packaging.

Description

The TMS320VC5471 integrates a DSP subsystem based on the TMS320C54x architecture and a RISC microcontroller subsystem based on the ARM7TDMI core as shown in Figure 2--1. The DSP subsystem includes 72K x 16-bit SRAM, a timer, a DMA controller, an external memory interface, and two McBSPs. The MCU subsystem includes three timers, general-purpose I/O, an external memory interface, and an Ethernet 10/100Base-T interface with a media-independent interface MII port.

TMS320VC5471 Features

• Dual CPU Processor Integrating a TMS320C54x™ DSP and an ARM7TDMI™ RISC MCU

• 16-Bit Low-Power DSP With 72K x 16-bit Integrated SRAM Operates at up to 100 MHz

• Smart Power Management and Low-Power Modes for DSP and MCU Subsystems

• Integrated DSP Subsystem Peripherals

   -- Two High-Speed, Full-Duplex Multichannel Buffered Serial Ports McBSPs Allowing the DSP Core to Interface Directly With CODECs

   -- Six-Channel Direct Memory Access DMA Controller Enabling Six Independent Block Transfers With No Intervention From the DSP

   -- ARM™ Port Interface API Provides 2K x 16-Bit Shared Memory Interface for Efficient Information Exchange Between the MCU Subsystem and the DSP Subsystem CPUs

   -- External Memory Interface

   -- Software-Programmable Wait-State Generator Capable of Extending External Bus Cycles By Up To 14 Machine Cycles

   -- One Software-Programmable Hardware Timer For Control Operations

   -- Programmable Phase-Locked Loop PLL Clock Generator

• ARM7TDMI RISC Microcontroller Core With 16K Bytes of Integrated SRAM and Enhanced Emulation Capabilities Operates at Up To 47.5 MHz

• Integrated MCU Subsystem Peripherals

   -- Ethernet Interface Module With 10/100 Mb/s IEEE 802.3 Ethernet Media Access Controller MAC

   -- Media Independent interface MII Port

   -- Universal Asynchronous Receiver/ Transmitter UART

   -- UART/IrDA Interface Which Supports the Slow Infrared SIR Protocol

   -- Serial Peripheral Interface

   -- Thirty-Six General-Purpose I/O Pins

   -- Inter-Integrated Circuit I2C Interface

   -- Two General-Purpose Timers

   -- One Watchdog Timer

   -- Interrupt Handler

   -- Interface to External Memory Supports Flash, SRAM, SDRAM, ROM

   -- Flexible Clock Management for MCU Peripherals

   -- Programmable Phase-Locked Loop PLL Clock Generator

• On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1† JTAG Boundary Scan Logic of DSP and MCU Cores

• Supports Scan-Based Emulation of DSP and MCU Cores

• 257-Ball MicroStar BGA™ GHK Suffix Package