CD4508BE

TEXAS INSTRUMENTS  CD4508BE  逻辑芯片, D型锁存器, 双路, 4位, 24DIP

The is a dual 4-bit Latch contains two identical 4-bit latches with separate STROBE, RESET and OD control. With the STROBE line in the high state, the data on the "D" inputs appear at the corresponding "Q" outputs provided the DISABLE line is in the low state. Changing the STROBE line to the low state locks the data into the latch. A high on the RESET line forces the outputs to a low level regardless of the state of the STROBE input. The outputs are forced to the high-impedance state for bus line applications by a high level on the DISABLE input.

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Individual master reset for each 4-bit latch

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3-state outputs with high-impedance state for bus line applications

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100% Tested for quiescent current at 20V

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Standardized, symmetrical output characteristics