AD9691BCPZRL7-1250

ADC Dual Pipelined 1.25GSPS 14Bit Serial 88Pin LFCSP T/R

Product Details

The AD9691 is a dual, 14-bit, 1.25 GSPS analog-to-digital converter ADC. The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. The device is designed for sampling wide bandwidth analog signals of up to 1.5 GHz.

The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.

Each ADC data output is internally connected to two digital downconverters DDCs. Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator NCO and four half-band decimation filters.

In addition to the DDC blocks, the AD9691 has several functions that simplify the automatic gain control AGC function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.

Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, four- or eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± input pins.

The AD9691 is available in a Pb-free, 88-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range.

Product Highlights

1. Low power consumption analog core, 14-bit, 1.25 GSPS dual analog-to-digital converter ADC with 1.9 W per channel.

2. Wide full power bandwidth supports IF sampling of signals up to 1.5 GHz.

3. Buffered inputs with programmable input termination eases filter design and implementation.

4. Flexible serial port interface SPI controls various product features and functions to meet specific system requirements.

5. Programmable fast overrange detection.

6. 12 mm × 12 mm 88-lead LFCSP.

Applications

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Communications wideband receivers and digital predistortion

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Instrumentation spectrum analyzers, network analyzers, integrated RF test solutions

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DOCSIS 3.x CMTS upstream receive paths

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High speed data acquisition systems

### Features and Benefits

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JESD204B Subclass 1 coded serial digital outputs

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1.9 W total power per channel default settings

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SFDR = 77 dBFS at 340 MHz

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SNR = 63.4 dBFS at 340 MHz AIN = −1.0 dBFS

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Noise density = −152.6 dBFS/Hz

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1.25 V, 2.50 V, and 3.3 V dc supply operation

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No missing codes

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1.58 V p-p differential full scale input voltage

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Flexible termination impedance

400 Ω, 200 Ω, 100 Ω, and 50 Ω differential

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1.5 GHz usable analog input full power bandwidth

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95 dB channel isolation/crosstalk

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See data sheet for additional features