66AK2G01

Multicore DSPARM KeyStone II System-on-Chip SoC

66AK2G0x is a family of heterogeneous multicore System-on-Chip SoC devices based on ’s field-proven Keystone II KS2 architecture. These devices address applications that require both DSP and ARM performance, with integration of high-speed peripheral and memory interfaces, hardware acceleration for network and cryptography functions, and high-level operating systems HLOS support.

Similar to existing KS2-based SoC devices, the 66AK2G0x enables both the DSP and ARM cores to master all memory and peripherals in the system. This architecture facilitates maximum software flexibility where either DSP- or ARM-centric system designs can be achieved.

The 66AK2G0x significantly improves device reliability by extensively implementing error correction code ECC in processor cores, shared memory, embedded memory in modules, and external memory interfaces. Full analysis of soft error rate SER and power-on-hours POH shows that the designated 66AK2G0x parts satisfy a wide range of industrial and automotive requirements.

Accompanied by the new Processor SDK, the 66AK2G0x development platform enables unprecedented ease-of-use with main line open source Linux, CCS 6.x, a wide range of OS-independent device drivers, as well as TI-RTOS that enables seamless task management across processor cores. The device also features advanced debug and trace technology with the latest innovations from TI and ARM, such as system trace and seamless integration of the ARM CoreSight components.

Secure boot can also be made available for anticloning and illegal software update protection. For more information about secure boot, contact your TI sales representative.

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**Processor Cores**:

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ARM Cortex-A15 Microprocessor Unit ARM A15 Subsystem at up to 600 MHz

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Supports Full Implementation of ARMv7-A Architecture Instruction Set

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Integrated SIMDv2 NEON Technology and VFPv4 Vector Floating Point

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32KB of L1 Program Memory

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32KB of L1 Data Memory

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512KB of L2 Memory

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Error Correction Code ECC Protection for L1 Data Memory ECC for L2 Memory

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Parity Protection for L1 Program Memory

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Global Timebase Counter GTC

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64-Bit Free-Running Counter That Provides Timebase for ARM A15 Internal Timers

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Compliant to ARM V7 MPCore Architecture for Generic Timers

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C66x Fixed- and Floating-Point VLIW DSP Subsystem at up to 600 MHz

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Fully Object-Code Compatible With C67x+ and C64x+ Cores

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32KB of L1 Program Memory

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32KB of L1 Data Memory

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1024KB of L2 Configurable as L2 RAM or Cache

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Error Detection for L1 Program Memory

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ECC for L1 Data Memory

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ECC for L2 Data Memory

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**Industrial Subsystem**:

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Up to Two Programmable Real-Time Unit and Industrial Communication Subsystems PRU-ICSS, Each Supports:

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Two Programmable Real-Time Units PRUs With Enhanced Multiplier and Accumulator, Each PRU Supports:

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16KB of Program Memory With ECC

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8KB of Data Memory With ECC

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CRC32 and CRC16 Hardware Accelerator

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20 × Enhanced GPIO

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Serial Capture Unit SCU, Supporting Direct Connection, 16-bit Parallel Capture, 28-bit Shift, MII_RT, EnDat 2.2 Protocol and Sigma-Delta Demodulation

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Scratch Pad and XFR Direct Connect

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64KB of General-Purpose Memory With ECC

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One Ethernet MII_RT Module with Two MII Ports Configurable for Connection With Each PRU; Support Multiple Industrial Communication Protocols

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Industrial Ethernet Peripheral IEP to Manage and Generate Industrial Ethernet Functions

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Built-In Universal Asynchronous Receiver and Transmitter UART 16550, With a Dedicated 192-MHz Clock to Support 12-Mbps PROFIBUS

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Built-In Industrial Ethernet 64-Bit Timer

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Built-In Enhanced Capture Module eCAP

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**Memory Subsystem**:

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Multicore Shared Memory Controller MSMC With 1024KB of Shared L2 RAM

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Provides High-Performance Interconnect to Internal Shared SRAM and DDR EMIF for Both ARM A15 and C66x Access

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Supports ARM I/O Coherency Where ARM A15 is Cache Coherent to Other System Masters Accessing the MSMC-SRAM or DDR EMIF

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Supports ECC on SRAM

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Up to 36-Bit DDR3L External Memory Interface EMIF

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Supports DDR3L at up to 800 MT/s

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Supports 4-GB Memory Address Range

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Supports 32-Bit SDRAM Data Bus With 4-bit ECC

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Supports 16-Bit and 32-Bit SDRAM Data Bus Without ECC

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General-Purpose Memory Controller GPMC

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Flexible 8- and 16-Bit Asynchronous Memory Interface With up to Four Chip Selects

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Supports NAND, NOR, Muxed-NOR, SRAM

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Supports General-Purpose Memory-Port Expansion With the Following Modes:

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Asynchronous Read and Write Access

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Asynchronous Read Page Access 4-, 8-, 16-Word16

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Synchronous Read and Write Access

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Synchronous Read Burst Access Without Wrap Capability 4-, 8-, 16-Word16

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Up to 16-Bit ECC Support for NAND Flash Using BCH Code t = 4, 8, or 16 or Hamming Code

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Error Location Module ELM

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Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm

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Supports 4-Bit, 8-Bit and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms

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Provides ECC Calculation Up to 16 bits for NAND Support

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**Network Subsystem NSS**:

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Ethernet MAC Subsystem EMAC

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One-Port Gigabit Ethernet: RMII, MII, RGMII

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Supports 10-, 100-, 1000-Mbps Full Duplex

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Supports 10-, 100-Mbps Half Duplex

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Supports Ethernet Audio Video Bridging eAVB

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Maximum Frame Size 2016 Bytes 2020 Bytes With VLAN

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Eight Priority Level QOS Support 802.1p

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IEEE 1588v2 2008 Annex D, Annex E, and

Annex F to Facilitate Audio Video Bridging 802.1AS Precision Time Protocol

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CPTS Module With Timestamping Support for IEEE 1588v2

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DSCP Priority Mapping IPv4 and IPv6

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MDIO Module for PHY Management

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Enhanced Statistics Collection

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Navigator Subsystem NAVSS

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Built-In Packet DMA Controller for Optimized Network Processing

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Built-In Queue Manager QM for Optimized Network Processing

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Supports up to 128 Queues

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2048 Buffers Supported in Internal Queue RAM

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Crypto Engine SA Supports:

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Crypto Function Library for AES, DES, 3DES, SHA1, MD5, SHA2-224 and SHA2-256 Operations

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Block Data Encryption Supported Through Hardware Cores

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AES With 128-, 192-, and 256-Bit Key Supports

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DES and 3DES With 1, 2, or 3 Different Key Support

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Programmable Mode Control Engine MCE

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Public Key Accelerator PKA With Elliptic Curve Cryptography

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Elliptic Curve Diffie–Hellman ECDH Based Key Exchange and Digital Signature ECDSA Applications

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Authentication for SHA1, MD5, SHA2-224 and SHA2-256

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Keyed HMAC Operation Through Hardware Core

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True Random Number Generator TRNG

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**Display Subsystem**:

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Supports One Video Pipe With In-Loop Scaling, Color Space

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Conversion and Background Color Overlay

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Input Data Format: BITMAP, RGB16, RGB24, RGB32, ARGB16, ARGB32, YUV420, YUV422, and RGB565-A8

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Supported Display Interfaces:

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MIPI DPI 2.0 Parallel Interface

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RFBI MIPI-DBI 2.0 up to QVGA at 30fps

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BT.656 4:2:2

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BT.1120 4:2:2 up to 1920 × 1080 at 30fps

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In-Loop Scaling Capability

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LCD Display Interface Supports:

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Active Matrix TFT

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Passive Matrix STN

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Grayscale

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TDM

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AC Bias Control

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Dither

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CPR

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**High-Speed Serial Interfaces**:

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PCI Express 2.0 Port with Integrated PHY:

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Single Lane Gen2-Compliant Port

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Root Complex RC and End Point EP Modes

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Up to Two USB 2.0 High-Speed Dual-Role Ports With Integrated PHYs, Support:

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Dual-role-device DRD Capability With:

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USB 2.0 Peripheral or Device at

HS 480Mbps and FS 12Mbps Speeds

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USB 2.0 Host at HS 480Mbps,

FS 12Mbps, and LS 1.5Mbps Speeds

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USB 2.0 Static Peripheral and Static Host Operations

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xHCI Controller With the Following Features:

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Compatible to the xHCI Specification revision 1.1 in Host Mode

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All Modes of Transfer Control, Bulk, Interrupt, and Isochronous

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15 Transmit TX, 15 Receive RX Endpoints EPs, and One Bidirectional EP0 Endpoint

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**Flash Media Interfaces**:

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QSPI With XIP and up to Four Chip Selects, Supports:

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Memory-Mapped Direct Mode of Operation for Performing FLASH Data Transfers and Executing Code From FLASH Memory XIP

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Supports up to 96 MHz

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Internal SRAM Buffer With ECC

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High Speed Read Data Capture Mechanism

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Two Multimedia Card MMC and Secure Digital SD Ports

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Supports JEDEC JESD84 v4.5-A441 and SD3.0 Physical Layer With SDA3.00 Standards

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MMC0 Supports 3.3-V I/O for:

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SD DS and HS Mode

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eMMC Mode HS-SDR and DDR

up to 48 MHz

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MMC1 Supports 1.8-V I/O Modes for eMMC, Including HS-SDR and DDR at up to 48 MHz With 4- and 8-Bit Bus Width

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**Audio Peripherals**:

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Three Multichannel Audio Serial Port McASP Peripherals

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Transmit and Receive Clocks up to 50 MHz

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Two Independent Clock Zones and Independent Transmit and Receive Clocks per McASP

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Up to 16-, 10-, 6-Serial Data Pins for McASP0, McASP1, and McASP2, Respectively

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Supports TDM, I2S, and Similar Formats

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Supports DIT Mode

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Built-In FIFO Buffers for Optimized System Traffic

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Multichannel Buffered Serial Port McBSP

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Transmit and Receive Clocks up to 50 MHz

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Two Clock Zones and Two Serial-Data Pins

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Supports TDM, I2S, and Similar Formats

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**Automotive Peripherals**:

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Two Controller Area Network CAN Ports

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Supports CAN v2.0 Part A, B ISO 11898-1 Protocol

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Bit Rates up to 1 Mbps

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Dual Clock Source

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ECC Protection for Message RAM

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One Media Local Bus MLB

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Supports Both 3-Pin Up to MOST50, 1024 × Fs and 6-Pin Up to MOST150, 2048 × Fs Versions of MediaLB Physical Layer Specification v4.2

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Supports All Types of Data Transfer Over 64 Logical Channels Synchronous Stream, Isochronous, Asynchronous Packet, Control Message

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Supports 3-Wire MOST 150 Protocol

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**Real-Time Control Interfaces**:

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Six Enhanced High Resolution Pulse Width Modulation eHRPWM Modules, Each Counter Supports:

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Dedicated 16-Bit Time-Base With Period and Frequency Control

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Two Independent PWM Outputs With Single Edge Operation

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Two Independent PWM Outputs With Dual-Edge Symmetric Operation

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One Independent PWM Output With Dual-Edge Asymmetric Operation

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Two 32-Bit Enhanced Capture Modules eCAP:

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Supports One Capture Input or One Auxiliary PWM Output Configuration Options

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4-Event Time-Stamp Registers Each 32-Bits

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Interrupt on Either of the Four Events

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Three 32-Bit Enhanced Quadrature Pulse Encoder Modules eQEP, Each Supports:

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Quadrature Decoding

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Position Counter and Control Unit for Position Measurement

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Unit Time Base for Speed and Frequency Measurement

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**General Connectivity**:

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Three Inter-Integrated Circuit I2C Interfaces, Each Supports:

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Standard up to 100 kHz and

Fast up to 400 kHz Modes

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7-Bit Addressing Mode

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Supports EEPROM Size Up to 4Mbit

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Four Serial Peripheral Interfaces SPI, Each Supports:

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Operates at up to 50 MHz in Master Mode and 25 MHz in Slave Mode

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Two Chip Selects

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Three UART Interfaces

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All UARTs are 16C750-Compatible and Operate at Up to 3M Baud

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UART0 Supports 8 Pins With Full Modem Control, With DSR, DTR, DCD, and RI Signals

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UART1 and UART2 are 4-Pin Interfaces

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General-Purpose I/O GPIO

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Up to 212 GPIOs Muxed With Other Interfaces

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Can be Configured as Interrupt Pins

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**Timers and Miscellaneous Modules**:

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Seven 64-Bit Timers:

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Two 64-Bit Timers Dedicated to ARM A15 and DSP Cores One Timer per Core

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Watchdog and General-Purpose GP

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Four 64-Bit Timers are Shared for General Purposes

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Each 64-Bit Timer Can be Configured as Two Individual 32-Bit Timers

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One 64-Bit Timer Dedicated for PMMC

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Two Timers Input/Output Pin Pairs

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Interprocessor Communication With:

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Message Manager to Facilitate Multiprocessor Access to the PMMC:

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Provides Hardware Acceleration for Pushing and Popping Messages to/from Logical Queues

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Supports Up to 64 Queues and 128 Messages

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Semaphore Module With Up to 64 Independent Semaphores and 16 Masters device cores

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EDMA With 128 2 × 64 Channels and

1024 2 × 512 PaRAM Entries

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**Keystone II System on Chip SoC Architecture**:

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Security

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Supports General-Purpose GP and High-Secure HS Devices

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Supports Secure Boot

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Supports Customer Secondary Keys

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4KB of One-Time Programmable OTP ROM for Customer Keys

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Power Management

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Integrated Power Management Microcontroller PMMC Technology

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Supports Primary Boot From UART, I2C, SPI, GPMC, SD or eMMC, USB Device Firmware Upgrade v1.1, PCIe, and Ethernet Interfaces

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Keystone II Debug Architecture With Integrated ARM CoreSight Support and Trace Capability

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**Operating Temperature TJ**:

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–40°C to 125°C Automotive

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–40°C to 105°C Extended

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0°C to 90°C Commercial

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