EP2A40F672C7

FPGA - 现场可编程门阵列 CPLD - APEX II 2560 Macro 492 IOs

* Programmable logic device PLD manufactured using a 0.15-m alllayer copper-metal fabrication process up to eight layers of metal * 1-gigabit per second Gbps True-LVDSTM, LVPECL, pseudo current mode logic PCML, and HyperTransportTM interface * Clock-data synchronization CDS in True-LVDS interface to correct any fixed clock-to-data skew * Enables common networking and communications bus I/O standards such as RapidIOTM, CSIX, Utopia IV, and POS-PHY Level 4 * Support for high-speed external memory interfaces, including zero bus turnaround ZBT, quad data rate QDR, and double data rate DDR static RAM SRAM, and single data rate SDR and DDR synchronous dynamic RAM SDRAM * 30% to 40% faster design performance than APEX 20KE devices on average * Enhanced 4,096-bit embedded system blocks ESBs implementing first-in first-out FIFO buffers, Dual-Port+ RAM bidirectional dual-port RAM, and content-addressable memory CAM * High-performance, low-power copper interconnect * Fast parallel byte-wide synchronous device configuration * Look-up table LUT logic available for register-intensive functions * High-density architecture * 1,900,000 to 5,250,000 maximum system gates * 38,400 logic elements LEs * Up to 1,146,880 RAM bits that can be used without reducing available logic * Low-power operation design * 1.5 V supply voltage * Copper interconnect reduces power consumption * MultiVolt I/O support for 1.5 V, 1.8 V, 2.5 V, and 3.3 V interfaces * ESBs offer programmable power-saving mode * I/O features * Up to 380 Gbps of I/O capability * 1-Gbps True-LVDS, LVPECL, PCML, and HyperTransport support on 36 input and 36 output channels that feature clock synchronization circuitry and independent clock multiplication and serialization/deserialization factors * Common networking and communications bus I/O standards such as RapidIO, CSIX, Utopia IV, and POS-PHY Level 4 enabled * 400-megabits per second Mbps Flexible-LVDS and HyperTransport support on up to 88 input and 88 output channels input channels also support LVPECL