SN74LV165DR

并联负载8位移位寄存器 PARALLEL-LOAD 8-BIT SHIFT REGISTERS

description

The ’LV165 parallel-load, 8-bit shift registers are designed for 2.7-V to 5.5-V VCC operation.

When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the SH/LD input. The ’LV165 feature a clock inhibit function and a complemented serial output QH.

EPICEnhanced-Performance Implanted CMOS 2-µ Process

Typical VOLPOutput Ground Bounce < 0.8 V at VCC, TA= 25°C

Typical VOHVOutput VOHUndershoot < 2 V at VCC, TA= 25°C

ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model C = 200 pF, R = 0

Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17

Package Options Include Plastic Small-Outline D, Shrink Small-Outline DB, Thin Shrink Small-Outline PW, Ceramic Flat W Packages, Chip Carriers FK, and J 300-mil DIPs