DS92LV16TVHG

TEXAS INSTRUMENTS  DS92LV16TVHG  总线, CAN, 收发器, 3.15 V, 3.45 V, PQFP

The is a Serializer/Deserializer SerDes pair transparently translates a 16-bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 16-bit or less bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width and connector size and pins. This SERDES pair includes built-in system and device test capability. The line loopback and local loopback features provide the following functionality: the local loopback enables the user to check the integrity of the transceiver from the local parallel-bus side and the system can check the integrity of the data transmission line by enabling the line loopback. The DS92LV16 incorporates BLVDS signalling on the high-speed I/O.

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Independent transmitter and receiver operation with separate clock, enable and power-down pins

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Hot plug protection power up high impedance and synchronization receiver locks to random data

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Line and local loopback modes

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Robust BLVDS serial transmission across backplanes and cables for low EMI

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No external coding required

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Internal PLL, no external PLL components required

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Loss of lock detection and reporting pin

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±100mV Receiver input threshold

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>2.5kV HBM ESD

Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.