74F280SCX

集成电路

General Description

The F280 is a high-speed parity generator/checker that accepts nine bits of input data and detects whether an

even or an odd number of these inputs is HIGH. If an even number of inputs is HIGH, the Sum Even output is HIGH. If an odd number is HIGH, the Sum Even output is LOW. The Sum Odd output is the complement of the Sum Even output.

得捷:
IC PARITY GEN/CHKER 9-BIT 14SOIC

艾睿:
Parity Generator/Checker 9-Bit 14-Pin SOIC N T/R

Verical:
Parity Generator/Checker 9-Bit 14-Pin SOIC N T/R

罗切斯特:
Parity Generator/Checker 9-Bit 14-Pin SOIC N T/R

Win Source:
9-Bit Parity Generator/Checker