IS61VVF409618B-7.5TQL

SRAM Chip Sync Dual 1.8V 72M-bit 4M x 18 7.5ns 100Pin TQFP

* Internal self-timed write cycle * Individual Byte Write Control and Global Write * Clock controlled, registered address, data and control * Burst sequence control using MODE input * Three chip enable option for simple depth expansion and address pipelining * Common data inputs and data outputs * Auto Power-down during deselect * Single cycle deselect * Snooze MODE for reduced-power standby * JTAG Boundary Scan for PBGA package * Power Supply:Vdd 1.8V + 5%, Vddq 1.8V + 5% * JEDEC 100-Pin TQFP, 119-pin PBGA, and 165- pin PBGA packages * Lead-free available.