CY7C1270V18-400BZC

36兆位的DDR -II + SRAM 2字突发架构（ 2.5周期读延迟） 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency

SRAM - Synchronous, DDR II Memory IC 36Mb 1M x 36 Parallel 400MHz 165-FBGA 15x17

得捷:
IC SRAM 36M PARALLEL 165FBGA

贸泽:
静态随机存取存储器 36M QDR2+ B2 2.5

艾睿:
SRAM Chip Sync Single 1.8V 36M-bit 1M x 36 0.45ns 165-Pin FBGA

Win Source:
36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency