SN74LVC1G79WDCKREP

触发器 Mil Enhance Sgl Pos- Edge-Trgrd D-Type

DESCRIPON/ORDERING INFORMATION

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

When data at the data D input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

FEATURES

• Supports 5-V VCC Operation

• Inputs Accept Voltages to 5.5 V

• Max tpd of 5 ns at 3.3 V

• Low Power Consumption, 10-µA Max ICC

• ±24-mA Output Drive at 3.3 V

• Ioff Supports Partial-Power-Down Mode Operation

• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

• ESD Protection Exceeds JESD 22

   – 2000-V Human-Body Model A114-A

   – 200-V Machine Model A115-A

   – 1000-V Charged-Device Model C101

  

SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS

• Controlled Baseline

• One Assembly/Test Site

• One Fabrication Site

• Available in Military –55°C/125°C Temperature Range1

• Extended Product Life Cycle

• Extended Product-Change Notification

• Product Traceability