ADS41B49IRGZT

14位/ 12位， 250MSPS ，超低功耗ADC模拟缓冲器 14-/12-Bit, 250MSPS, Ultralow-Power ADC with Analog Buffers

The is an Analog-to-digital Converter ADC featuring integrated analog input buffers. This is member of the ultralow-power ADS4xxx ADC family, this device use innovative design techniques to achieve high dynamic performance and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance. The devices support both double data rate DDR low-voltage differential signalling LVDS and parallel CMOS digital output interfaces.

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Digital gain and offset correction

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Integrated high-impedance analog input buffer

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Ultralow power

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High dynamic performance

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Output interface

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Double data rate LVDS with programmable swing and strength

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Programmable gain for SNR, SFDR trade-OFF

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DC offset correction

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Supports low input clock amplitude

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Green product and no Sb/Br