TAS5504

4 通道数字音频 PWM 处理器

The is a four channel digital pulse width modulator PWM that provides both advanced performance and a high level of system integration. The TAS5504 is designed to interface seamlessly with most audio digital signal processors. The TAS5504 automatically adjusts control configurations in response to clock and data rate changes and idle conditions. This enables the TAS5504 to provide an easy to use control interface with relaxed timing requirements.

The TAS5504 can drive four channels of H-bridge power stages. Texas Instruments H-bridge parts TAS5111, TAS5112, or TAS5182 + FETs are designed to work seamlessly with the TAS5504. The TAS5504 supports both single-ended or bridge tied load configurations. The TAS5504 also provides a high performance differential output to drive an external differential input analog headphone amplifier such as the TPA112.

The TAS5504’s uses an AD modulation operating at a 384-kHz switching rate for 48-, 96-, and 192-kHz data. The 8x over sampling combined with the 5th order noise shaper provides a broad flat noise floor and excellent dynamic range from 20 Hz to 20 kHz.

The TAS5504 is clock slave only device. The TAS5504 receives MCLK, SCLK and LRCLK from other system components. The TAS5504 accepts master clock rates of 128, 192, 256, 384, 512, and 768 Fs. The TAS5504 accepts a 64-Fs bit clock.

The TAS5504 allows for extending the dynamic range by providing a power supply volume control PSVC output signal.

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Audio Input / Output

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Automatic Master Clock Rate and Data Sample Rate Detection

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Four Serial Audio Input Channels

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Four PWM Audio Output Channels

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Headphone PWM Output to Drive an External Differential Amplifier Like the TPA112

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PWM Outputs Support Single Ended and Bridge Tied Loads

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32-, 38-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz Sampling Rates

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Data Formats: 16-, 20-, or 24-bit input Data Left, Right and I2S,

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64 x Fs Bit Clock Rate

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128, 192, 256, 384, 512, and 768 x Fs Master Clock Rates Up to a Maximum of 50 MHz

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Audio Processing

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48-Bit Processing Architecture With 76 bits of Precision for Most Audio Processing Features

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Volume Control Range +36 dB to &@150;127 dB

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Master Volume Control Range of +18 dB to –100 dB

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Four Individual Channel Volume Control Range of +18-dB to –127-dB

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Programmable Soft Volume and Mute Update Rates

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Four Bass and Treble Tone Controls with ±18-dB Range, Selectable Corner Frequencies, and 2nd Order Slopes

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L, R, and C

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LS, RS

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Configurable Loudness Compensation

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Two Dynamic Range Compressors With Two Thresholds, Two Offsets, and Three Slopes

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Seven Bi-quads Per Channel

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8x4 Input Crossbar Mixer. Each Signal Processing Channel Input Can Be Any Ratio of the Eight Input Channels

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4x2 Output Mixer – Channels 1 and 2. Each Output Can Be Any Ratio of Any Two Signal Processed Channels

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4x3 Output Mixer – Channels 3 and 4. Each Output can be Any Ratio of Any Three Signal Processed Channels

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Three Coefficient Sets Stored on the Device Can be Selected Manually or Automatically Based on Specific Data Rates

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DC Blocking Filters

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Able to Support a Variety of Bass Management Algorithms

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PWM Processing

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32-Bit Processing PWM Architecture With 40 Bits of Precision

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8x Oversampling With 5th Order Noise Shaping at 32 — 48 kHz, 4x Oversampling at 88.2 kHz, and 96 kHz and 2x Oversampling at 176.4 kHz and 192 kHz

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>102-dB Dynamic Range

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THD+N < 0.1%

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20 — 20-kHz Flat Noise Floor for 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz Data Rates

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Digital De-emphasis for 32-, 44.1-, and 48-kHz Data Rates

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Flexible Automute Logic With Programmable Threshold and Duration for Noise Free Operation

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Intelligent AM Interference Avoidance System Provides Clear AM Reception

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Power Supply Volume Control PSVC Support for Enhanced Dynamic Range in High Performance Applications

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Adjustable Modulation Limit

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General Features

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Automated Operation With an Easy to Use Control Interface

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I2C Serial Control Slave Interface

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Integrated AM Interference Avoidance Circuitry

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Single 3.3-V Power Supply

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64-Pin TQFP Package

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5-V Tolerant Inputs