TL16PC564B

具有 64 字节 FIFO、PCMCIA 接口的单路 UART

The /BLV is designed to provide all the functions necessary for a Personal Computer Memory Card International Association PCMCIA universal asynchronous receiver transmitter UART subsystem interface. This interface provides a serial-to-parallel conversion for data to and from a modem coder-decoder/digital signal processor CODEC/DSP function to a PCMCIA parallel data-port format. A computer central processing unit CPU, through a PCMCIA host controller, can read the status of the asynchronous communications element ACE interface at any point in the operation. Reported status information includes the type of transfer operation in process, the status of the operation, and any error conditions encountered.

Attribute memory consists of a 256-byte card information structure CIS and eight 8-byte card configuration registers CCR. The CIS, implemented with a dual-port random-access memory DPRAM, is available to both the host CPU and subsystem modem, as are the CCRs. This DPRAM is used in place of the electrically erasable programmable read-only memory EEPROM normally used for the CIS. At power up, attribute memory is initialized by the subsystem.

The TL16PC564B/BLV uses a TL16C550 ACE-type core with an expanded 64 × 11 receiver first-in-first-out FIFO memory and a 64 × 8 transmitter FIFO memory. The receiver trigger logic flags have been adjusted in order to take full advantage of the increased capacity when in the extended mode. In addition, eight of the UART registers have been mapped into the subsystem modem memory space as read-only registers. This allows the subsystem to read UART status information.

A subsystem-selectable serial-bypass mode has been implemented to allow the subsystem to bypass the serial portion of the UART and write directly to the receiver FIFO and read directly from the transmitter FIFO. Interrupt operation is not affected in this mode.

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Integrated Asynchronous Communications Element ACE Compatible With PCMCIA PC Card Standard Release 2.01

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Consists of a Single TL16C550 ACE Plus PCMCIA Interface Logic

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Provides Common I-Bus/Z-Bus Microcontroller Inputs for Most Intel™ and Zilog™ Subsystems

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Fully Programmable 256-Byte Card Information Structure CIS and 8-Byte Card Configuration Register CCR

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Adds or Deletes Standard Asynchronous Communication Bits Start, Stop and Parity to or From Serial Data Stream

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Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts

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Subsystem Selectable Serial-Bypass Mode Provides Subsystem With Direct Parallel Access to the FIFOs

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Fully Programmable Serial-Interface Characteristics:

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5-, 6-, 7-, or 8-Bit Characters

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Even-, Odd-, or No-Parity Bit Generation and Detection

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1-, 1 1/2-, or 2-Stop Bit Generation

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Baud-Rate Generation

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Fully Prioritized Interrupt System Controls

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Modem Control Functions

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Provides TL16C450 Mode at Reset Plus Selectable Normal TL16C550 Operation or Extended 64-Byte FIFO Mode

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Selectable Auto-RTS\ Mode Deactivates RTS\ at 14 Bytes in 550 Mode and at 56 Bytes in Extended 550 Mode

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Selectable Auto-CTS\ Mode Deactivates Serial Transfers When CTS\ is Inactive

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Available in 100 Pin Thin Quad Flatpack PZ Package or 100-Ball GGM MicroStar BGA™ Package

Intel is a registered trademark of Intel System, Inc. Zilog is a registered trademark of Zilog Incorporated MicroStar BGA is a trademark of Texas Instruments Incorporated.