CD74HCT163E

TEXAS INSTRUMENTS  CD74HCT163E  芯片, 74HCT CMOS逻辑器件

The is a 4-bit high speed CMOS Binary Counter with synchronous reset. The look-ahead carry feature simplifies serial cascading of the counters. Both count enable inputs PE and TE must be high to count. The TE input is gated with the Q outputs of all four stages so that at the maximum count the terminal count TC output goes high for one clock period. This TC pulse is used to enable the next cascaded stage. It reset synchronously with the clock. Counting and parallel presetting are both accomplished synchronously with the negative-to-positive transition of the clock. A low level on the synchronous parallel enable input, SPE, disables counting operation and allows data at the P0 to P3 inputs to be loaded into the counter provided that the setup and hold requirements for SPE are met. Two count enables, PE and TE, in each counter are provided for n-bit cascading. In the counter reset action occurs regardless of the level of the SPE\, PE and TE inputs.

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Synchronous counting and loading

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Two count enable inputs for n-bit cascading

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Balanced propagation delay and transition times

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Significant power reduction compared to LSTTL logic ICs

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High noise immunity

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Direct LSTTL input logic compatibility

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CMOS Input compatibility

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10 LSTTL Load standard outputs

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15 LSTTL Load bus driver outputs