CY7C1250KV18-400BZI

36兆位的DDR II + SRAM 2字突发架构（ 2.0周期读延迟） 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency

SRAM - Synchronous, DDR II+ Memory IC 36Mb 1M x 36 Parallel 400MHz 165-FBGA 13x15

得捷:
IC SRAM 36M PARALLEL 165FBGA

贸泽:
静态随机存取存储器 36MB 1Mx36 1.8v 400MHz DDR II 静态随机存取存储器

艾睿:
SRAM Chip Sync Single 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin FBGA Tray

Chip1Stop:
SRAM Chip Sync Single 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin FBGA Tray

DeviceMart:
IC SRAM DDR-II+ CIO 36MB 165FBGA