GS81302DT20E-500

静态随机存取存储器 1.8 or 1.5V 8M x 18 144M

* 2.5 Clock Latency * Simultaneous Read and Write Sigma Quad™ Interface * JEDEC-standard pin out and package * Dual Double Data Rate interface * Byte Write controls sampled at data-in time * Burst of 4 Read and Write * Dual-Range On-Die Termination ODT on Data D, Byte Write BW, and Clock K, K inputs * 1.8 V +100/–100 mV core power supply * 1.5 V or 1.8 V HSTL Interface * Pipelined read operation * Fully coherent read and write pipelines * ZQ pin for programmable output drive strength * Data Valid Pin QVLD Support * IEEE 1149.1 JTAG-compliant Boundary Scan * 15 mm x 17 mm, 165 FPBGA * RoHS-compliant 165-bump BGA package available * 1MB product Family