CY2305SXI-1

1个基准输入,5个输出,带内部反馈

The is a Zero Delay Buffer designed to distribute high speed clocks. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input and drives out five low skew clocks. The 1H version of each device operate at up to 133MHz frequency and has higher drive than the devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. If all output clocks are not required, bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes.

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Zero input-output propagation delay

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One input drives nine outputs

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Compatible with Pentium-based systems

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60ps Typical cycle-to-cycle jitter high drive

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85ps Typical output-to-output skew