CY7C1270KV18-400BZXC
36兆位的DDR II + SRAM 2字突发架构( 2.0周期读延迟) 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency
SRAM - 同步,DDR II+ 存储器 IC 36Mb(1M x 36) 并联 165-FBGA(13x15)
立创商城:
CY7C1270KV18-400BZXC
得捷:
IC SRAM 36MBIT PARALLEL 165FBGA
艾睿:
SRAM Chip Sync Single 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin FBGA Tray
Chip1Stop:
SRAM Chip Sync Single 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin FBGA Tray