74AC11074

具有清零和预设功能的双路上升沿 D 类触发器

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset or clear input sets or resets the outputs regardless of the levels of the other inputs. When and are inactive high, data at the data D input that meets the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock CLK pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The is characterized for operation from -40°C to 85°C.

 

 

 

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Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise

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EPICTM Enhanced-Performance Implanted CMOS 1-m Process

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500-mA Typical Latch-Up Immunity at 125°C

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Package Options Include Plastic Small-Outline D and Thin Shrink Small-Outline PW Packages, and Standard Plastic 300-mil DIPs N

 

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