IS61LPS102418A-200TQLI

SRAM Chip Sync Dual 3.3V 18M-bit 1M x 18 3.1ns 100Pin TQFP

DESCRIPTION

The ISSIIS61LPS/VPS51236A, IS61LPS/VPS102418A, and IS61LPS/VPS25672A are high-speed, low-power synchronous static RAMs designed to provide burstable, high performance memory for communication and networking applications. The IS61LPS/VPS51236A is organized as 524,288 words by 36 bits, the IS61LPS/VPS102418A is organized as 1,048,576 words by 18 bits, and the IS61LPS/VPS25672A is organized as 262,144 words by 72 bits. Fabricated withISSI"s advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and control

• Burst sequence control using MODE input

• Three chip enable option for simple depth expansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

   LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%

   VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5%

• JEDEC 100-Pin TQFP, 119-ball PBGA, 165-ball PBGA, and 209-ball x72 packages

• Lead-free available