IS42S16320D-7TLI

INTEGRATED SILICON SOLUTION ISSI  IS42S16320D-7TLI  芯片, 存储器, SDRAM, SDR, 512MB, 3.3V, 54TSOPII

The is a high speed CMOS, dynamic Random Access Memory RAM designed to operate in either 3.3 or 2.5V Vdd/Vddq memory systems, depending on the DRAM option. It is internally configured as a quad-bank DRAM with a synchronous interface. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 512Mb SDRAM 536870912-bit has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide pre-charge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row pre-charge initiated at the end of the burst sequence is available with the AUTOpre-charge function enabled. Pre-charge one bank while accessing one of the other three banks will hide the pre-charge cycles and provide seamless, high-speed, random-access operation.

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Clock frequency - 143MHz

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Fully synchronous, all signals referenced to a positive clock edge

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Internal bank for hiding row access/pre-charge

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LVTTL interface

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Programmable burst length

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Programmable burst sequence - sequential/interleave

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Auto refresh CBR

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Self refresh

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8K Refresh cycle/64ms

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Random column address every clock cycle

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Programmable CAS latency

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Burst read/write and burst read/single write operations capability

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Burst termination by burst stop and pre-charge command

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Speed - 7ns