AD4010BCPZ-RL7

Single Channel Single ADC SAR 500KSPS 18Bit Serial 10Pin LFCSP EP T/R

Product Details

The AD4010 is a low noise, low power, high speed, 18-bit, 500 kSPS precision successive approximation register SAR analog-to-digital converter ADC. It incorporates ease of use features that lower the signal chain power, reduce signal chain complexity, and enable higher channel density. The high-Z mode, coupled with a long acquisition phase, eliminates the need for a dedicated high power, high speed ADC driver, thus broadening the range of low power precision amplifiers that can drive this ADC directly while still achieving optimum performance. The input span compression feature enables the ADC driver amplifier and the ADC to operate off common supply rails without the need for a negative supply while preserving the full ADC code range. The low serial peripheral interface SPI clock rate requirement reduces the digital input/output power consumption, broadens processor options, and simplifies the task of sending data across digital isolation.

Operating from a 1.8 V supply, the AD4010 samples an analog input IN+ between 0 V to VREF with respect to a ground sense IN− with VREF ranging from 2.4 V to 5.1 V. The AD4010 consumes only 3.5 mW at 500 kSPS and achieves ±2.0 LSB INL maximum, guaranteed no missing codes at 18 bits with 95 dB SNR. The reference voltage is applied externally and can be set independently of the supply voltage. The SPI-compatible versatile serial interface features seven different modes including the ability, using the SDI input, to daisy-chain several ADCs on a single 3-wire bus and provides an optional busy indicator. The AD4010 is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply.

The AD4010 is available in a 10-lead LFCSP with operation specified from −40°C to +125°C. The device is pin compatible with the 18-bit, 2 MSPS AD4003.

**Applications**

.

Automatic test equipment

.

Machine automation

.

Medical equipment

.

Battery-powered equipment

.

Precision data acquisition systems

### Features and Benefits

.

Throughput: 500 kSPS maximum

.

INL: ±2.0 LSB maximum

.

Guaranteed 18-bit no missing codes

.

Low power

.

2.5 mW at 500 kSPS VDD only

.

70 μW at 10 kSPS, 3.5 mW at 500 kSPS total

.

SNR: 95 dB typical at 1 kHz, TBD dB typical at 100 kHz

.

THD: -120 dB typical at 1 kHz, TBD dB typical at 100 kHz

.

Ease of use features reduce system power and complexity

.

Input overvoltage clamp circuit

.

Reduced nonlinear input charge kickback

.

High-Z mode

.

Long acquisition phase

.

Input span compression

.

Fast conversion time allows low SPI clock rates

.

SPI-programmable modes, read/write capability, status word

.

Pseudo differential single-ended analog input range: 0 V to VREF with VREF between 2.4 V to 5.1 V

.

Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface

.

SAR architecture: no latency/pipeline delay

.

Guaranteed operation: -40°C to 125°C

.

Serial interface SPI-/QSPI-/MICROWIRE-/DSP-compatible

.

Ability to daisy-chain multiple ADCs and busy indicator

.

10-lead package: 3 mm × 3 mm LFCSP