FT601Q-T

FTDI  FT601Q-T  接口桥接器, USB 到 FIFO, 3 V, 3.6 V, QFN, 76 引脚, -40 °C

The is a high performance USB 3.0-to-FIFO Interface Bridge Chip can be used in those applications which require high data throughput such as imaging devices and multi-channel FIFO ADC or DAC devices etc. The FIFO interface can support multi-voltage I/O and operating frequencies of 66.67 or 100MHz. The 100MHz only for 2.5 and 3.3V. There are 2 different proprietary synchronous bus protocols supported; one FIFO bus protocol is called the "Multi-Channel FIFO" bus protocol and the other is the "245 Synchronous FIFO" bus protocol. The USB 3.0 protocol controller manages the data stream from the device USB control endpoint. It handles the USB protocol requests generated by the USB host controller and the commands for controlling the functional parameters of the FIFO in accordance with the USB 3.0 specification. This unit is used to manage all PIPE data or buffers in the FIFO memory; the data is sent or received through the FIFO protocol layer.

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Control/bulk/interrupt

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Up to 8 configurable endpoints PIPEs

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Built-in 16kB FIFO data buffer RAM

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Supports remote wakeup capability

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Configurable GPIO support

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Internal LDO 1.0V regulator

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Integrated power-ON-reset circuit

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User programmable USB descriptors

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Supports battery charging spec. BC1.2

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Integrated power-on-reset circuit

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Extended operating temperature range: -40°C to 85°C

Drivers and Software available to download from www.ftdichip.com