74HCT107N

NXP  74HCT107N  触发器, 复位, 互补输出, 负沿, JK, 19 ns, 73 MHz, 4 mA, DIP, 14 引脚

The is a dual negative edge triggered JK Flip-flop featuring individual J and K inputs, clock CP\\ and reset R\\ inputs and complementary Q and Q\ outputs. The reset is an asynchronous active low input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the high-to-low clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

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TTL Input levels

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Complies with JEDEC standard No. 7A