MT46V32M16P-5B IT

MICRON  MT46V32M16P-5B IT  芯片, 存储器, SDRAM, DDR, 512MB, 66TSOP

The is a Double Data Rate DDR SDRAM uses double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe DQS is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during reads and by the memory controller during writes. DQS is edge-aligned with data for reads and centre-aligned with data for writes. The x16 offering has two data strobes, one for the lower -byte and one for the upper -byte.

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Differential clock inputs

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Commands entered on each positive CK edge

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DLL to align DQ and DQS transitions with CK

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Four internal banks for concurrent operation

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Auto refresh - 64ms, 8192-cycle

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Longer-lead TSOP for improved reliability OCPL

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Concurrent auto precharge option supported