AD9517-3A/PCBZ

ANALOG DEVICES  AD9517-3A/PCBZ  评估板, 12输出, 时钟发生器, 2.8GHZ VC

Low phase noise, phase-locked loop PLL On-chip VCO tunes from 1.75 GHz to 2.25 GHz External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic revertive and manual reference switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable 2 pairs of 1.6 GHz LVPECL outputs Each output pair shares a 1-to-32 divider with coarse phase delay Additive output jitter: 225 fs rms Channel-to-channel skew paired outputs of <10 ps 2 pairs of 800 MHz LVDS clock outputs Each output pair shares two cascaded 1-to-32 dividers with coarse phase delay Additive output jitter: 275 fs rms Fine delay adjust Δt on each LVDS output Each LVDS output can be reconfigured as two 250 MHz CMOS outputs Automatic synchronization of all outputs on power-up Manual output synchronization available Available in a 48-lead LFCSP