MT46V16M16TG-75

DRAM Chip DDR SDRAM 256Mbit 16Mx16 2.5V 66Pin TSOP Tray

MT46V64M4 – 16 MEG x 4 x 4 BANKS

MT46V32M8 – 8 MEG x 8 x 4 BANKS

MT46V16M16 – 4 MEG x 16 x 4 BANKS

General Description

The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad bank DRAM.

Features

•VDD= +2.5V ±0.2V, VDDQ = +2.5V ±0.2V

• Bidirectional data strobe DQS transmitted/received with data, i.e., source-synchronous data capture x16 has two – one per byte

• Internal, pipelined double data rate DDR architecture; two data accesses per clock cycle

• Differential clock inputs CK and CK#

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-aligned with data for WRITEs

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Data mask DM for masking write data x16 has two – one per byte

• Programmable burst lengths: 2, 4, or 8

• Auto Refresh and Self Refresh Modes

• Longer-lead TSOP for improved reliability OCPL

• 2.5V I/O SSTL_2 compatible

• Concurrent auto precharge option supported

•tRAS lockout supported tRAP =tRCD