TPS51200

具有适用于 DDR2、DDR3、DDR3L 和 DDR4 的 VTTREF 缓冲基准的 3A 灌/拉 DDR 终端稳压器

The device is a sink and source double data rate DDR termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The maintains a fast transient response and requires a minimum output capacitance of only 20 μF. The supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT bus termination.

In addition, the provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 suspend to RAM for DDR applications.

The is available in the thermally efficient 10-pin VSON thermal pad package, and is rated both Green and Pb-free. It is specified from –40°C to +85°C.

For all available packages, see the orderable addendum at

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Input Voltage: Supports 2.5-V Rail and 3.3-V Rail

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VLDOIN Voltage Range: 1.1 V to 3.5 V

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Sink and Source Termination Regulator Includes Droop Compensation

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Requires Minimum Output Capacitance of 20-μF Typically 3 × 10-μF MLCCs for Memory Termination Applications DDR

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PGOOD to Monitor Output Regulation

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EN Input

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REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider

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Remote Sensing VOSNS

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±10-mA Buffered Reference REFOUT

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Built-in Soft Start, UVLO, and OCL

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Thermal Shutdown

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Supports DDR, DDR2, DDR3, DDR3L, Low-Power DDR3, and DDR4 VTT Applications

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10-Pin VSON Package With Thermal Pad