CDCP1803

具有可编程除法器的 1:3 LVPECL 时钟缓冲器

The clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0] with minimum skew for clock distribution. The CDCP1803 is specifically designed for driving 50-Ω transmission lines.

The CDCP1803 has three control terminals, S0, S1, and S2, to select different output mode settings; see for details. The CDCP1803 is characterized for operation from –40°C to 85°C. For use in single-ended driver applications, the CDCP1803 also provides a VBB output terminal that can be directly connected to the unused input as a common-mode voltage reference.

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Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs

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Programmable Output Divider for Two LVPECL Outputs

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Low-Output Skew 15 ps Typical

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VCC Range 3 V–3.6 V

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Signaling Rate Up to 800-MHz LVPECL

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Differential Input Stage for Wide Common-Mode Range

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Provides VBB Bias Voltage Output for Single-Ended Input Signals

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Receiver Input Threshold ±75 mV

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24-Terminal QFN Package 4 mm × 4 mm

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Accepts Any Differential Signaling:

LVDS, HSTL, CML, VML, SSTL-2, and

Single-Ended: LVTTL/LVCMOS