EL4584CS

水平同步锁相，为4fsc Horizontal Genlock, 4FSC

The EL4584 is a PLL Phase Lock Loop sub system, designed for video applications but also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS compatible Pixel Clock CLK OUT which is a multiple of the TV horizontal scan rate and phase locked to it.

Features

• 36MHz, general purpose PLL

•4FSCbased timing use the EL4585 for 8FSC

• Compatible with EL4583 sync separator

• VCXO, Xtal, or LC tank oscillator

• < 2ns jitter VCXO

• User controlled PLL capture and lock

• Compatible with NTSC and PAL TV formats

• 8 pre-programmed TV scan rate clock divisors

• Selectable external divide for custom ratios

• Single 5V, low current operation

• Pb-Free plus anneal available RoHS compliant

Applications

• Pixel clock regeneration

• Video compression engine MPEG clock generator

• Video capture or digitization

• PIP Picture in Picture timing generator

• Text or graphics overlay timing