74LVC1G11GW,125
AND Gate 1Element 3IN CMOS 6Pin TSSOP T/R
The 74LVC1G11GW is a single 3-input AND Gate, the input can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment. Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
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- 5V Tolerant inputs for interfacing with 5V logic
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- High noise immunity
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- Complies with JEDEC standard - JESD8-7, JESD8-5 and JESD8-B/JESD36
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- ±24mA Output drive VCC = 3V
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- ESD protection - HBM JESD22-A114F exceeds 2000V, MM JESD22-A115-A exceeds 200V
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- CMOS low power consumption
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- Latch-up performance exceeds 250mA
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- Direct interface with TTL levels