74LVC126APW

74系列逻辑芯片/74LVC126APW

DESCRIPTION

The 74LVC126A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V.

The 74LVC126A consists of four non-inverting buffers/line drivers with 3-state outputs nY which are controlled by the output enable input nOE. A LOW at nOE causes the outputs to assume a high-impedance OFF-state.

FEATURES

• 5 V tolerant inputs/outputs for interfacing with 5 V logic

• Wide supply voltage range from 1.2 to 3.6 V

• CMOS low power consumption

• Direct interface with TTL levels

• Inputs accept voltages up to 5.5 V

• Complies with JEDEC standard no. 8-1A

• ESD protection:

   HBM EIA/JESD22-A114-A exceeds 2000 V

   MM EIA/JESD22-A115-A exceeds 200 V.

• Specified from −40 to +85 °C and −40 to +125 °C.