SN74ABT18652PM
18位总线收发器和寄存器扫描测试设备 SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS
This scan test device with an 18-bit bus transceiver and register is a member of the Texas Instruments SCOPE testability IC family. This device supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the four-wire test access port TAP interface.
In the normal mode, this device is an 18-bit bus transceiver and register that allows for multiplexed transmission of data directly from the input bus or from the internal registers. It can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers and registers.
Data flow in each direction is controlled by clock CLKAB and CLKBA, select SAB and SBA, and output-enable OEAB and OEBA\\\\ inputs. For A-to-B data flow, data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus transparent mode. When SAB is high, stored A data is selected for presentation to the B bus registered mode. When OEAB is high, the B outputs are active. When OEAB is low, the B outputs are in the high-impedance state. Control for B-to-A data flow is similar to that for A-to-B data flow but uses CLKBA, SBA, and OEBA\ inputs. Since the OEBA\ input is active-low, the A outputs are active when OEBA\ is low and are in the high-impedance state when OEBA\ is high. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74ABT18652.
In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary scan test operations according to the protocol described in IEEE Std 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input TDI, test data output TDO, test mode select TMS, and test clock TCK. Additionally, the test circuitry can perform other testing functions, such as parallel signature analysis on data inputs and pseudorandom pattern generation from data outputs. All testing and scan operations are synchronized to the TAP interface.
Additional flexibility is provided in the test mode through the use of two boundary scan cells BSCs for each I/O pin. This allows independent test data to be captured and forced at either bus A or B. A PSA/COUNT instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful.
