SNJ54HC109FK

具有清零和预置端的双路负边沿触发式 J-K 触发器 20-LCCC -55 to 125

description/ordering information

These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset PRE or clear CLR inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive high, data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock CLK pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.

● Wide Operating Voltage Range of 2 V to 6 V

● Low Input Current of 1 µA Max

● High-Current Outputs Drive Up To 10 LSTTL Loads

● Low Power Consumption, 40-µA Max ICC

● Typical tpd = 12 ns

● ±4-mA Output Drive at 5 V