74AC11478

具有三态输出的八路双组 D 类触发器

The is an 8-bit dual-rank synchronizer circuit designed specifically for data synchronization applications in which the normal setup and hold time specifications are frequently violated.

Synchronization of two digital signals operating at different frequencies is a common system problem. This problem is typically solved by synchronizing one of the signals to the local clock through a flip-flop. This solution, however, causes the setup and hold time specifications associated with the flip-flop to be violated. When the setup or hold time of a flip-flop is violated, the output response is uncertain. A flip-flop is metastable if its output hangs up in the region between VIL and VIH. The metastable condition lasts until the flip-flop recovers into one of its two stable states. With conventional flip-flops, this recovery time can be longer than the specified maximum propagation delay.

The problem of metastability is typically solved by adding an additional layer of synchronization. This dual-rank approach is employed in the 74AC11478. The probability of the second stage entering the metastable state is exponentially reduced by this dual-rank architecture. The 74AC11478 provides a one-chip solution for system designers in asynchronous applications.

The 74AC11478 is characterized for operation from -40°C to 85°C.

 

 

[dagger] Data presented at the D inputs requires two clock cycles to appear at the Q outputs.

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Specifically Designed for Data Synchronization Applications

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3-State Outputs Drive Bus Lines Directly

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Flow-Through Architecture Optimizes PCB Layout

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Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise

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EPIC TM Enhanced-Performance Implanted CMOS 1-m Process

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Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

EPIC is a trademark of Texas Instruments Incorporated.