CD74AC109M96

TEXAS INSTRUMENTS  CD74AC109M96  触发器, 差分, 正沿, JK, 10.3 ns, 100 MHz, 24 mA, SOIC, 16 引脚

The is a dual positive-edge-triggered J-K Flip-flop with set and reset. It contains two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset PRE\\ or clear CLR\\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive high, data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. This versatile flip-flop can perform as toggle flip-flops by grounding K\ and tying J high. It also can perform as D-type flip-flop if J and K\ are tied together.

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Speed of Bipolar F, AS and S, with significantly reduced power consumption

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Balanced propagation delays

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±24mA Output drive current

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SCR-Latchup-resistant CMOS process and circuit design

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Green product and no Sb/Br