IS61NLF25636A-6.5TQ

256K x 36 and 512K x 18 9Mb, FLOW THROUGH "NO WAIT" STATE BUS SRAM

DESCRIPTION

The 9 Meg "NLF/NVF" product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, "no wait" state, device for networking and communications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabricated with ISSI"s advanced CMOS technology.

Incorporating a "no wait" state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.

FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single Read/Write control pin

• Clock controlled, registered address, data and control

• Interleaved or linear burst sequence control using MODE input

• Three chip enables for simple depth expansion and address pipelining

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 119-ball PBGA, and 165- ball PBGA packages

• Power supply:

   NVF: VDD 2.5V ± 5%, VDDQ 2.5V ± 5%

   NLF: VDD 3.3V ± 5%, VDDQ 3.3V/2.5V ± 5%

• JTAG Boundary Scan for PBGA packages

• Industrial temperature available

• Lead-free available